1. Field of the Invention
The present invention relates in general to a high-speed NRZ data bit synchronizer in which a transition density of NRZ data varies widely, and more particularly to a high-speed bit synchronizer with a multi-stage control structure in which frequency synchronization is performed within a desired frequency range in such a manner that a low pass filter (integrator) cannot output a maximum or minimum value, and phase synchronization is then performed together with the frequency synchronization. The synchronization is performed in such a manner that a voltage controlled oscillator can generate an oscillating frequency synchronously with a multiple of a frequency of an external reference clock pulse, so that the voltage controlled oscillator, such as a semiconductor integrated circuit voltage controlled oscillator, is available even though it has an unstable frequency and, although the number of transitions of rapid input data bits is small, the data and the clock can be stably recovered.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a block diagram of a conventional bit synchronizer. As shown in this drawing, the conventional bit synchronizer comprises a phase comparator 11, a low pass filter (integrator) 12, and a voltage controlled oscillator (referred to hereinafter as VCO) 13.
In the conventional bit synchronizer, as shown in FIG. 1, the phase comparator 11 has an output connected directly to an input of the low pass filter (integrator) 12 (see U.S. Pat. No. 4,400,667, Belkin, U.S. Pat. No. 4,422,176, Summers, and U.S. Pat. No. 4,535,459, Hogge).
Generally, a phase comparator for bit synchronization has an output variable according to the number of transitions of input NRZ data, or a gain variable according to a transition density of the input NRZ data, resulting in a loop gain of a phase locked loop (referred to hereinafter as PLL) circuit being varied according to a bit pattern of the input NRZ data or the probability that the transitions occur in the input NRZ data (see D. L. Duttweiler, "The Jitter Performance of Phase-Locked Loops Extracting Timing from Baseband Data Waveforms", The Bell System Technical Journal, Jan. 1976).
Thus, a higher loop gain of the PLL circuit results in unstable operation of the bit synchronizer when the number of data transitions is large, and a lower loop gain of the PLL circuit results in unstable operation of the bit synchronizer when the number of data transitions is small.
Also in the conventional bit synchronizer, the low pass filter (integrator) 12 of the PLL circuit is operated to detect a magnitude of the low frequency component including a direct current (DC) component from an output pulse from the phase comparator 11, and to output the detected magnitude to the VCO 13. When the output pulse from the phase comparator 11 has the narrow width or a bit rate of the NRZ data is high, the magnitude of the low frequency component cannot be detected therefrom by the low pass filter (integrator) 12 because it is very small, resulting in unstable operation of the PLL circuit (see U.S. Pat. No. 4,400,667, Belkin, U.S. Pat. No. 4,422,176, Summers, and U.S. Pat. No. 4,535,459, Hogge).
To solve the above problem, a recently developed bit synchronizer comprises separately a VCO frequency monitoring PLL circuit and a bit synchronizing PLL circuit for data recovery, for performing separate frequency and phase synchronizations (see U.S. Pat. No. 4,787,097, R. P. Rizzo). Alternatively, a bit synchronizer comprises a PLL circuit including a low pass filter (integrator) for simultaneously controlling a VCO to enhance the performance of the bit synchronization (see U.S. Pat. No. 4,942,370, T. Shigemori).
However, in such bit synchronizers, a phase comparator or a frequency comparator has an output connected directly to an input of the low pass filter (integrator), in a similar manner to that in FIG. 1. For this reason, such bit synchronizers cannot overcome the above-mentioned problems.
Further, in the conventional bit synchronizers, making a DC gain of the low pass filter (integrator) of the PLL circuit larger causes the low pass filter (integrator) to output a maximum or minimum value in a transient lock-in state, resulting in an unstable free-run frequency of the VCO. This results in unstable operation of the PLL circuit. Making the DC gain of the low pass filter (integrator) of the PLL circuit smaller to prevent such instability causes the locking range of the PLL circuit to be reduced. As a result, the loop gain of the PLL circuit is varied according to the bit pattern of the input NRZ data.